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[VHDL-FPGA-Verilog] taix_fee

Description: verilog HDL编写的出租车计费系统-verilog HDL prepared Taxi Accounting System
Platform: | Size: 553984 | Author: yukiflower | Hits:

[VHDL-FPGA-Verilog] 8251Verilog

Description: 通用串行异步收发器8251的Verilog HDL源代码,经过仿真验证。 -Universal Serial Asynchronous Receiver Transmitter 8251 the Verilog HDL source code, through simulation.
Platform: | Size: 15360 | Author: 钟兵 | Hits:

[VHDL-FPGA-Verilog] qiangdaqi(auto)

Description: 用verilog hdl硬件描述语言实现多人抢答器功能，有计时，计分，报警等功能。-Using hardware description language verilog hdl people realize Answer feature, have timing, scoring and alarm functions.
Platform: | Size: 266240 | Author: 杨操 | Hits:

[VHDL-FPGA-Verilog] fft1024

Description: 1024点fft verilog hdl-1024-point fft verilog hdl
Platform: | Size: 24576 | Author: | Hits:

[Software Engineering] Verilog_HDL

Description: Verilog HDL程序设计教程，非常实用，对学习Verilog非常有用。
Platform: | Size: 10857472 | Author: 汪毅 | Hits:

[VHDL-FPGA-Verilog] 8051core-Verilog

Description: 利用verlilog hdl语言编程，完成了8051内核，非常值得学习硬件描述语言的人看看！-Verlilog hdl programming language to use to complete the 8051 core, very much worth learning hardware description language of the people to see!
Platform: | Size: 53248 | Author: 小方 | Hits:

[Other] verilog_std

Description: Verilog HDL的标准，比较详细的语法说明-Verilog HDL standards, a more detailed description of the grammar
Platform: | Size: 1429504 | Author: 甲壳虫 | Hits:

[VHDL-FPGA-Verilog] SystemOfTaxiFeeBasedOnVerilogHDL

Description: 摘 要：以上海地区的出租车计费器为例，利用Verilog HDL语言设计了出租车计费器，使其具有时间 显示、计费以及模拟出租车启动、停止、复位等功能，并设置了动态扫描电路显示车费和对应时间，显示 了硬件描述语言Verilog—HDL设计数字逻辑电路的优越性。源程序经MAX+PLUS Ⅱ软件调试、优 化，下载到EPF1OK10TC144—3芯片中，可应用于实际的出租车收费系统。 关键词：Verilog HDL；电子自动化设计；硬件描述语言；MAX+PLUSⅡ-Abstract: Shanghai taxi meter as an example, the use of Verilog HDL language designed taxi meter so that it will have the time display, billing, as well as analog taxis to start, stop, reset and other functions, and set up a dynamic scanning circuit shows that the fare and the corresponding time, shows the hardware description language Verilog-HDL design of the superiority of digital logic circuits. Source by MAX+ PLUS Ⅱ software debugging, optimization, downloaded to EPF1OK10TC144-3 chip, can be applied to the actual taxi fare collection system. Keywords: Verilog HDL electronic design automation hardware description language MAX+ PLUS Ⅱ
Platform: | Size: 211968 | Author: 杨轶帆 | Hits:

[Software Engineering] VerilogHDLDigtialSystemDesign

Description: Verilog HDL数字设计与综合 夏宇闻译（第二版）-Verilog HDL digital design and synthesis Xia Wen translation (second edition)
Platform: | Size: 538624 | Author: 杨轶帆 | Hits:

[Software Engineering] FromAlgorithmToAchievmentOfHardware

Description: 从算法设计到硬线逻辑的实现 Verilog HDL牛人编写的有关经典书籍，其中包含很多例子-From algorithm design to hard-line Verilog HDL logic realize cattle were prepared by the classic book, which contains many examples
Platform: | Size: 830464 | Author: 杨轶帆 | Hits:

[Other] VerilogHDLGuide

Description: Verilog HDL Guide,是学习Verilog不错的教程,是CHM格式的-Verilog HDL Guide, is a good tutorial to learn Verilog is the CHM format
Platform: | Size: 1723392 | Author: 李成有 | Hits:

[ARM-PowerPC-ColdFire-MIPS] verilog

Description: 8bit alu use verilog hdl
Platform: | Size: 8192 | Author: 周微微 | Hits:

[VHDL-FPGA-Verilog] VerilogHDL

Description: 王金明：《Verilog HDL 程序设计教程》程序 把程序部分单独列出来 让你跳过大段文字直接接触源程序 -Wang Jinming:
Platform: | Size: 175104 | Author: 唐星 | Hits:

[Other Embeded program] Freq

Description: 简易数字频率计，用Verilog HDL编写的，基于Quartus II实现，结构清晰，功能较为全面，能满足简单的频率测量要求-Simple digital frequency meter, using Verilog HDL prepared, based on the Quartus II realize, clear structure, function is more comprehensive to meet the simple requirements of frequency measurement
Platform: | Size: 404480 | Author: 余翔 | Hits:

[VHDL-FPGA-Verilog] altera_ram

Description: 本程序对如何使用altera系列芯片片上ram进行实例演示，采用Verilog HDL语言编写，并使用modelsim与quartus联合进行功能仿真。本原码是红色逻辑开发板的试验程序，值得一看。-This procedure of how to use the altera series chip-chip ram for example demonstration, using Verilog HDL language, and using ModelSim and Quartus functional simulation carried out jointly. Primitive code is red logic development board of the pilot program, worth a visit.
Platform: | Size: 180224 | Author: panyouyu | Hits:

[Other] OtherVerilogHDLSynthesisAPracticalPrimer

Description: Verilog HDL Synthesis, A Practical Primer 学习Verilog HDL一本很不错的英文书，比较透彻-Verilog HDL Synthesis, A Practical Primer learning Verilog HDL a very good English books, more thorough
Platform: | Size: 4994048 | Author: 文字 | Hits:

[VHDL-FPGA-Verilog] VerilogHDLBasicExperiment

Description: verilog HDL 基础实验源码，比较实用-verilog HDL experimental basis for source code, more practical
Platform: | Size: 1006592 | Author: mosquito | Hits:

[VHDL-FPGA-Verilog] VerilogHDLIntegrationExperiment

Description: verilog HDL综合实验源代码，比较实用-Comprehensive Experiment verilog HDL source code, more practical
Platform: | Size: 543744 | Author: mosquito | Hits:

[MPI] clock

Description: 用Verilog HDL写的数字时钟,已经在开发板上验证过的,绝对原创,使用数码管进行显示!-Written using Verilog HDL Digital Clock, has been verified in the development of on-board absolute originality, the use of digital tube display!
Platform: | Size: 2048 | Author: 吴俊泉 | Hits:

[VHDL-FPGA-Verilog] uartverlog

Description: 占用资源少的verilog HDL uart接口；采用固定波特率115200，可以修改程序中的分频来修改波特率，模式为1个启始位，8位数据位，1个停止位；带1字节缓存；当缓存空时输出空信号-Occupy fewer resources verilog HDL uart interface adopted a fixed baud rate of 115200, can modify the procedure to modify the baud rate frequency, the model of a start bit, 8 data bits, 1 stop bit with one word section of the cache when the cache empty space-time output signal
Platform: | Size: 2048 | Author: 张诚 | Hits:
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